The present invention relates to an adaptive clock duty cycle controller for adaptively controlling and regulating the duty cycle of a digital clock signal.
The present invention controls a logic device such as a logic inverter or a logic buffer to produce a stable clock signal having a known duty cycle. A stable and known duty cycle is required in many applications where signal fidelity of clocked data is important. One such area of application is in the generation of bipolar digital telephone interface pulses for digital telephone hierarchies such as DS1, DS3, etc.
A conventional clock duty cycle controller used for maintaining a duty cycle of 50 percent, for example, doubles the frequency of the clock signal and then divides that doubled frequency by two using a flip-flop, such that the conventional duty cycle controller operates at an integer multiple of a selected frequency which is obtained by an oscillator. The conventional duty cycle controller is disadvantageous since the current consumption is high due to the high frequency of the oscillator, and the output of the oscillator varies which results in an unstable duty cycle.
In addition, the conventional duty cycle controller is limited as to the type of logic devices which may be used for outputting the duty cycle signal. More particularly, logic devices operate within specified frequency ranges and when a logic device of a particular technology is operating near maximum capability, it may not be possible to operate such a logic device at two times the clock frequency.